rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad6402 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 if transceiver subsystem features on-chip regulator pll demodulator on-chip vco no trims excellent sensitivity 28-lead ssop package applications dect/pwt/wlan tdma fm/fsk systems general description the ad6402 is a complete transceiver subsystem for use in high bit rate radio systems employing fm or fsk modulation. it is optimized for use in time domain multiple access (tdma) systems with communications rates of approximately 1 mbps. the ad6402 integrates key functions, including vcos and a low drop-out voltage regulator. the ad6402 operates directly from an unregulated battery supply of 3.1 v to 4.5 v and pro- vides a regulated voltage output which can be used for vco supply regulation on a companion rf chip such as the ad6401. the ad6402 transceiver consists of a mixer, integrated if bandpass filter, if limiter with rssi detection, vco, pll demodulator and a low dropout voltage re gulator. on receive, it downconverts an if signal in the 110 mhz range to a second if frequency, this frequency being determined by the demodu- lator reference divide ratios. it then filters, amplifies, and de- modulates this signal. the ad6402 provides a filtered baseband functional block diagram pll demod
C2C rev. 0 ad6402Cspecifications ad6402ars parameter conditions min typ max units if bandpass filter center frequency rejection refin = 13.824 mhz, refsel <0.2 v cc 20.736 mhz f o 3.0 mhz 7 dbc f o 4.7 mhz 13 dbc f o 6.0 mhz 16 dbc stop band rejection 30 dbc receiver sensitivity fm modulated 576 khz, fm deviation 288 khz C80 dbm bt = 0.5, demod output snr = 10 db, r s = 150 w rssi low v out = 0.2 v, r s = 150 w C85 dbm high v out = 1.8 v, r s = 150 w C5 dbm slope see figure 4 20 mv/db output impedance 4k w demodulator gain at data filter output 1.2 1.55 v/mhz offset referred to slref C200 +200 mv lock time from sleep mode 200 m s from rxlock mode 20 m s data filter op amp gain 2 slew rate c load = 30 pf 8 v/ m s gain bandwidth c load = 30 pf 15 mhz output swing low 0.2 v output swing high v cc C0.2 v output impedance 50 w if vco frequency note 1 131 mhz ssb phase noise @ 5 mhz offset C139 dbc/hz output power differential r load = 300 w C12 dbm 2nd harmonic C22 db 3rd harmonic C24 db transmit filter op amp open loop gain 75 db unity gain bandwidth c load = 30 pf 12 mhz output slew rate c load = 30 pf 5 v/ m s minimum input voltage 1v maximum input voltage v cc C0.2 v minimum output voltage 0.2 v maximum output voltage v cc C0.2 v power control logical high threshold 0.8 v cc v logical low threshold 0.2 v cc v turn-on response time v cc steady state 0.5 m s voltage reference slref 1.3 1.5 v supply regulator output voltage for battery voltages from 3.1 v to 4.5 v 2.75 2.95 v turn-on time 1 mv settling, c load = 100 nf 200 m s line regulation 200 mv battery step; 5 mv settling 1 m s load regulation 10 m a to 30 ma step; 5 mv settling 200 m s power supply all v cc at 2.85 v supply current rxlockp 30 ma rxlock 17 ma rxdemod 26 ma transmit 6 ma standby 300 m a sleep 10 m a notes 1 using test tank circuit as shown. specifications subject to change without notice. obsolete
ad6402 C3C rev. 0 warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad6402 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. recommended operating conditions vbat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 vC4.5 v ifvcc1, ifvcc2, pllvcc . . . . . . . . . . . . . . . . . . . .2.85 v operating temperature range . . . . . . . . . . . C25 c to +85 c absolute maximum ratings* supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5 v storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature, soldering (60 sec) . . . . . . . . . . . . +300 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended rating conditions for extended periods may affect device reliability. thermal characteristics: 28-lead ssop package: q ja = 109 c/w. ordering guide temperature package model range description ad6402ars C25 c to +85 c 28-lead ssop ad6402ars-reel C25 c to +85 c 28-lead ssop pin configuration 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) 28 27 26 25 24 23 22 21 ad6402 txoutb ifin ifvcc1 refsel txout modout fmmod2 fmmod1 ifvcc2 rssi ifgnd vcognd vco vreg vbat ctl3 ctl2 slref pllvcc pllgnd ctl1 cfilt coff rext dout refin pllout dfilp pin function descriptions pin mnemonic function 1 txoutb transmit if vco buffer inverting output 2 modout frequency modulator filter op amp output 3 fmmod2 frequency modulator filter op amp noninverting input 4 fmmod1 frequency modulator filter op amp inverting input 5 vcognd if vco ground 6 vco if vco tank connection 7 vreg regulated supply output for rf vco (supplies internal if vco, mode control, bandgap reference, and coff buffer) 8 vbat battery supply voltage input to internal regulator and coff charge pump 9 ctl3 mode control input 3, cmos logical level 10 ctl2 mode control input 2, cmos logical level 11 ctl1 mode control input 1, cmos logical level 12 cfilt pll demodulator loop filter capacitor 13 coff pll demodulator frequency offset voltage track/hold capacitor 14 rext external current-setting resistor 15 refin baseband reference frequency input, 100 mv p-p, ac coupled 16 pllout pll demodulator output 17 dfilp data filter voltage-follower input 18 dout data filter voltage-follower output 19 slref pll demodulator output dc reference voltage 20 pllvcc pll demodulator and data filter supply input 21 pllgnd pll demodulator and data filter ground 22 ifvcc2 if limiter supply input 1 23 rssi rssi output 24 ifgnd if stage, mixer, band pass filter, if vco buffer, tx op amp, mode control, and regulator ground 25 ifin if mixer input, z o = 150 z 26 ifvcc1 if mixer, limiter 1, if filter, if vco buffer 27 refsel reference frequency select; if = 1.5 or 2.5 reference frequency, cmos logical level input 28 txout transmit if vco buffer output obsolete
ad6402 C4C rev. 0 ad6402 vco vcognd txout txoutb modout fmmod2 fmmod1 1nf 1nf smv 1204-36 39nh 8pf 47pf 1.2k w 4.7nf 1nf smv 1204-37 240 w 150pf vcci 330 w 100pf 330 w 180pf 330 w txmod txif+ txif v tune figure 1. overview the ad6402 forms the basis of a highly integrated rf trans- ceiver with the benefits of increased sensitivity and wide dy- namic range that a dual-conversion architecture provides. the ic contains a low dropout voltage regulator to isolate the if and demodulator vcos from variation in the battery voltage, such as power-supply transients caused by the pa. the ad6402 also provides control circuitry that allows subcircuits to be turned off and on as necessary to minimize power consumption. operation during receive the ad6402 contains the second mixer, integrated second-if bandpass filter, logarithmic-limiting amplifier, and pll de- modulator. a saw if bandpass filter is usually required at the if input in order to provide channel selectivity. the placement of the saw filter in the signal path between the ad6402 and the rf section and the partitioning of the receivers rf and if receive circuits minimizes the leakage around the saw filter and maximizes the rf to if isolation. the output of the saw filter enters the ad6402 via the second downconversion mixer. this mixer is a high gain, doubly- balanced gilbert-cell type. the mixer downconverts the signal to the second if, which is 1.5 or 2.5 the reference frequency. this multiple is determined by the state of the refsel pin. an on-chip two section bandpass filter provides additional selectiv- ity to provide attenuation of adjacent channels. the vco con- trol voltage output of the pll demodulator tunes this filter to the second if. the bandpass filters output enters a successive-detection loga- rithmic-limiting if amplifier. the rssi detectors are distrib- uted across the entire if strip, including the mixer, and provide 80 db rssi range. the if strips limiting gain also exceeds 80 db. the rssi signal is low-pass filtered and proceeds off-chip to the baseband subsystem. the limited output of the logarith- mic amplifier enters a pll demodulator, which provides de- modulation of the received signal. the pll uses an integrated vco with no external components. operation during transmit the transmit signal path consists of a low-pass filter that can be user configured for antialiasing of a baseband transmit signal. an if vco, which should be tuned to a frequency equal to the receive if frequency plus the desired demodulator input fre- quency, may be open-loop modulated by the transmit signal for fm and fsk schemes. the receive if mixer uses high side mixing and therefore the if vco should be set to a frequency equal to the sum of the if frequency plus the frequency of the pll de modulator input as defined by the reference clock divider ratios. the transmit if vco uses an external tank circuit. this signal is upconverted to the transmit frequency in the rf mixer sec- tion of the radio. using a transmit if vco prevents two prob- lems: feedback from the pa at the rf frequency does not cause distortion in the modulating circuit because the frequencies are widely separated and the if tank circuit can be optimized for modulation linearity. the output of the transmit vco passes through buffer amplifier and leaves the ad6402 via an optional lc filter between the rf and if ics. the output of the lc filter may then be fed to a transmit upconversion mixer for conversion to the final rf frequency. onboard voltage regulation the ad6402 contains a low dropout voltage regulator to spe- cifically isolate the vcos and synthesizer from the voltage kick that occurs when a power amplifier switches on and the battery voltage abruptly drops. the ad6402 uses an integral vertical pnp pass transistor. the regulator in the ad6402 if ic supplies the voltage for the vcos on both the rf section and ad6402. the other sections of the ad6402 should be powered from an independently regu- lated source at 2.85 v. since the vcos are isolated from this source, possible problems due to vco supply pushing are con- siderably reduced. frequency control the ad6402 requires an external synthesizer to provide the control voltages for the tank circuit of the if vco. normally this will be the if section of a dual synthesizer controlling both if and rf frequency generation. it is recommended that the vco on the rf section implement the channel selection on transmit and receive; the vco on the ad6402 may therefore operate at a fixed frequency. this ac- complishes two goals: first, the if vco being modulated can be optimized for modulation linearity and the rf vco can be optimized for tuning range, and second, feedback from the pa at will not couple into the modulating circuit to cause spurious responses. all key sections of the ad6402 may be powered up or down as necess ary to minimize power consumption and maximize battery life. obsolete
ad6402 C5C rev. 0 table i. power management functionality pll pll pll tl1 ctl2 ctl3 bias lock dmod ref reg rx vco mode 0 0 0 C C C off off C C sleep 0 0 1 C C C off on C C standby 010ononoffononoffon rxlock 1 x 0 on off on on on on on rxdmod 1 0 1 off off off on on off on transmit 111ononoffonononon rxlockp ref rx pll dmod pll bias ref reg pll lock vco ifvcc1 ifvcc2 rssi dout dflip pllout pllvcc pllgnd rext cfilt refsel fmmod2 fmmod1 modout txoutb txout ctl1 ctl2 ctl3 vcognd vco slref vreg vbat ifgnd ifin coff refin reg cp /2 cp /3,/5 pd figure 2. power management scheme the ad6402 has six operating modes: sleep, standby, rxlock, rxdmod, transmit and rxlockp. these are summarized in table i. the blocks referred to in table i are shown also in figure 4. these modes are described as follows: sleep: the entire device is shut down. standby: all functions except the regulator are shut down. rxlock: the device locks to a local reference clock using the lock pll. the lock charge pump and divid- ers are powered up. the vco is also powered up. rxdmod: in this mode the lock charge pump and loop dividers are shut down. the receive mixer, if strip, reference and demodulator are powered up. transmit: this mode enables the vco and transmit op amp. the reference and regulator are also enabled. rxlockp: this mode may be used in a prior to timeslot, i.e., the slot before the actual active receive timeslot. in this mode, after lock has been achieved in the rxlock mode, the receive mixer, vco and if strip may then be indepen- dently powered up from the demodulator loop. this can result is power savings, since the de- modulator may be powered down during the if vco lock acquisition time. obsolete
ad6402 C6C rev. 0 demodulator operation the pll itself uses two loops: one for rapid frequency acquisi- tion and a second for demodulation. the first, or frequency- acquisition loop, locks the vco to a noninteger multiple of the system clock, either 3/2 or 5/2 (using one fixed /2 and one pro- grammable /3 or /5 divider). this allows not only a choice of if and system clocks but also prevents blocking of the receiver by keeping integer multiples of the system clock out of the if passband. once locked, this loop voltage is stored on an external capacitor and this sets the free-running frequency of the vco during demodulation. the first loop is opened and, using the second loop and phase detector, the pll compares the free-running frequency of its vco to the frequency of the incoming if. the vco is then fast frequency locked, and slow phase locked to the incoming if. preconditioning of the pll to the local reference clock facilitates the fast frequency lock to the received if. the pll now generates a baseband voltage proportional to the fre- quency deviation of the received signal. the demodulator uses a third-order pll to track the incoming modulation signal. a simplified diagram of the demodulator is shown in figures 3a and 3b. the loop bandwidth and damping factor can be adjusted by changing the values of c and r as indicated. an internal pole is present on the demodulator loop at approximately 9 mhz. for a loop w n of 800 khz, values of 910 pf and 330 w respectively are optimum. the loop band- width will approximately scale inversely as the square root of the value of c. to preserve a satisfactory damping factor, r should be adjusted linearly with the loop bandwidth. at low loop band- widths however the value of c offset must also be increased to enable the loop to lock to the reference frequency during prior to receive time slots. applications the ad6402 is optimized for use in applications where a data rate of the order of 1 megabit per second is required and the modulation scheme employed is constant envelope, i.e., fm or fsk. because the demodulator uses a track and hold technique that locks to an externally supplied reference clock, the device is optimized for use in tdma systems. if used in continuous demodulation applications, the dc offset hold voltage on the demodulator differential amplifier will ultimately leak away, resulting in the average dc value of the demodulator output eventually limiting against the supply rail. in a tdma system, the voltage on the capacitor is refreshed just before the active pllout coff coffset 1.4k w 500 w 34pf vco 220
ad6402 C7C rev. 0 supply current levels when not allocated to an active transmit or receive timeslot in a tdma system.. the respective transmit and receive blocks can be turned on only as needed thereby reducing power consumption and extending battery life of handheld terminals. the component selection in figure 5 is explained as follows: the if input is driven from the output of a saw filter via an impedance matching circuit as shown. this matching minimizes the insertion loss of the filter and follows the filter manufactur- ers recommendations. the tank circuit shown uses two varactor diodes. one diode (d3) is biased by the output of the if pll loop filter and ensures that the if vco frequency is correctly centered. the second diode is provided to enable a modulation signal, which is generated at the output of the on-chip op amp (modout), to be coupled into the vco tank and thereby implement a modulation of the vco frequency. in the case of dect, the if vco control loop is opened while the vco is being modulated by the transmit bit stream. the loop is opened by tri-stating the output of the if vco pll charge pump. the exact component values used around the modulation am- plifier will be determined by the amount of attenuation required for suppression of baseband transmit spurii and images. these artifacts are usually present if the baseband fsk signal is gener- ated by a romdac. in most instances a second or third order bessel or butterworth filter will be required. a capacitor to ground is required to be connected to coff. this capacitor stores the demodulator charge-pump voltage required to lock the demodulator vco to the reference fre- quency. the dynamic response of the demodulator loop is con- trolled by selection of the values for c45 and r22 which are connected in series to cfilt. these components determine the ifvcc1 ifvcc2 dout dfilp c71 1nf c44 100nf vrf cp reg ref cp /3,/5 pd rssi pllout pllvcc pllgnd rext cfilt refsel fmmod2 fmmod1 modout txoutb txout ctl1 ctl2 ctl3 vcognd vco slref vreg vbat ifgnd ifin coff refin c30 150pf r16 330 w c28 1nf c29 1nf l11 39nh c41 8pf c42 47pf r26 1.2k w c50 4.7nf c25 1nf r21 240 w d2 d3 c43 100nf vif c44 1nf v cc 12pf c10 1nf l7 100nh l6 150nh 10 9 8 7 6 1 2 3 4 5 l5 150nh c69 1nf cp c52 100pf r28 330 w c51 180pf r32 330 w r70 c32 100nf c45 131nf r22 330 w c13 1nf c31 r17 10k w c11 100pf vrf r10 2k w r9 1k w c14 68pf c12 33pf r30 2k w c58 47pf rxbb rssi c4 3.3nf r8 4.7k w ad6402 smv 1204-37 smv 1204-36 txif txif+ ifc0 ifc1 ifc2 vref v tune b4535 ifin txbb r35 4.7k w rclk figure 5. application circuit for dect gfsk transceiver transfer characteristic of the loop filter and hence the lock time, settling time and bandwidth of the loop. rext should use the recommended value as shown. finally, the demodulator is followed by a voltage follower, which is configured as a data filter. this data filter is used to bandlimit the fm noise generated in the demodulator. it also attenuates undesired adjacent channel interferers. the compo- nent values chosen will be a trade-off between the amount of band limiting required and attenuation of the in-band desired signal. dect application circuit notes (figure 5) 1. signal description vrf: regulated supply voltage; nominal value 2.85 v. v cc : unregulated battery voltage; 3.1 vC4.5 v vtune: synthesizer control voltage; range dependent on loop filter and synth charge pump compliance. txbb: baseband transmit modulation voltage; typically slref 0.7 v rclk: reference clock for pll demodulator; 13.824 mhz (2nd if frequency = (n/m) frclk where n = 3 or 5, and m = 2. maximum 2nd if = c.26 mhz) 2. typical if input sensitivity referred to the input of saw filter for the above application will be C72 dbm. 3. txbb filter is user configurable. in the above application, the filter is implemented to remove images generated by rom dac baseband signal generators. other implementations are possible including passive pulse shaping circuits which elimi- nate the need for such filtering. obsolete
ad6402 C8C rev. 0 outline dimensions dimensions shown in inches and (mm). c3155C12C7/97 printed in u.s.a. 28-lead small shrink outline package (rs-28) 28 15 14 1 0.407 (10.34) 0.397 (10.08) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) pin 1 seating plane 0.008 (0.203) 0.002 (0.050) 0.07 (1.79) 0.066 (1.67) 0.0256 (0.65) bsc 0.078 (1.98) 0.068 (1.73) 0.015 (0.38) 0.010 (0.25) 0.009 (0.229) 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) 8 0 evaluation board an evaluation board is available for the ad6402. this board facilitates test and measurement of the subsystem. parameters such as sensitivity, aci, cci, demodulator gain, demodulator offset, etc., can be quickly evaluated using this board. contact 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 pllout dout slref pllvcc gnd ifvcc2 rssi gnd ifvcc1 refsel nc modin modout ctl1 ctl2 ctl3 vbatx vbat gnd vreg nc = no connect j1 figure 6. evaluation board header ad6402 20 1 j1 synth in txoutb txout ifin refin note: synth in, txoutb, txout, ifin and refin connected via sma connectors figure 7. evaluation board connectors your local adi sales office or adi representative for further details on pricing and availability of the evaluation boards. header connections details are shown in figure 6 and available signals are shown in figure 7. a schematic for the evaluation board is shown in figure 8. 8k w 0.1
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